1. Field of the Invention
The present invention relates to a method for manufacturing an isolation region and more particularly to a method for manufacturing a trench isolation in a semiconductor device.
2. Description of the Related Art
As the density of integrated circuits increases, the dimension of an isolation region between active regions in semiconductor devices decrease. With this trend, the conventional local oxidation of silicon (LOCOS) method for isolating active regions, which forms a field oxide layer by using a thermal oxidation technique, confronts the limit in the effective isolation length, thereby degrading characteristics of the isolation region. Furthermore, the conventional LOCOS method possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird's beak.
According to the disadvantages for LOCOS isolation structures mentioned above, an isolation technique using trenches has been developed. Generally, the trench isolation includes the steps of etching a silicon substrate to form a trench, depositing an oxide layer by using a chemical vapor deposition (CVD) process to fill up the trench, providing the oxide layer with a planarized surface using a chemical mechanical polish (CMP) process, and removing the oxide layer upon the active regions.
According to this technique, the semiconductor substrate is etched at a predetermined depth, thereby providing excellent characteristics of the device isolation. Furthermore, the field oxide layer is formed using a CVD technique, so that the device isolation region that is defined by a photolithography process can be maintained throughout.
However, the trench isolation technique described above has some drawbacks. For example, as shown in FIG. 1, a conventional trench isolation structure is illustrated. Residual polysilicon 104a, 104b are formed on the sharp corners of the interconnection between the trench isolation 102 and the surface of the silicon substrate 100. The residual polysilicon 104a, 104b are usually formed in the deposition and etching processes of the polysilicon used as gate electrodes. They may conduct neighboring gate electrodes and cause various problems of short circuit. It is therefore desirable in the art to provide a method for manufacturing trench isolation structures without the problems mentioned above. It is towards those goals that the present invention is specifically directed.